Riviera-PRO is particularly relevant for evaluation where simulation forms part of a systematic verification process. The question is not only whether a design runs, but also how failures are isolated, results assessed and tests repeated across the team.
Technical focus
Aldec lists mixed-language simulation, extensive debugging views, and code and functional coverage features. The manufacturer’s documentation also describes UVM and VHDL verification libraries such as OSVVM and UVVM. Which features are available to your project must be checked against the selected product configuration and specific version.
Measure value against the verification process
A useful evaluation includes at least one typical functional test, a deliberately failing test and a small regression. Compare how clearly the failure is reported, the route to its cause and the ability to reproduce results. A single runtime measurement with unknown options is insufficient for a tool decision.
What should be clear before the first run
- Language versions and constructs used in the design and testbench.
- Versions of verification libraries and compiled FPGA/IP models.
- Operating system, batch invocation and licence provisioning.
- Required assertions, coverage data and report formats.
- Number of concurrent users and regression runs.
Working with the editor
For teams using Sigasi Visual HDL, Sigasi documents a task for external Riviera-PRO compilation. It can feed diagnostics back into the editing workflow. Simulation still needs a testbench, elaboration configuration and execution. The shared workflow explains the separation.
Limits of a product statement
Documented library support does not demonstrate that your complete project has already been tested. Coverage values likewise assess only the chosen metric. Requirements, test quality and justified exclusions remain the responsibility of the development team.
Use our verification application notes for a bounded introduction, or request a Riviera-PRO evaluation with your specific requirements.