These definitions are deliberately brief. A shared vocabulary makes team discussions easier; specific tool details and language rules belong in the relevant documentation.
- HDL
- Hardware Description Language: a language for describing hardware structures and behaviour. VHDL and Verilog/SystemVerilog are important examples.
- RTL
- Register Transfer Level: an abstraction describing registers, combinational logic and data transfers between clock cycles. Not every HDL description is synthesisable RTL.
- FPGA
- Field-Programmable Gate Array: a programmable logic device whose function is defined by a configuration. Implementation tools process the HDL description to produce that configuration.
- ASIC
- Application-Specific Integrated Circuit: an integrated circuit designed for a particular application. Changes after fabrication need to be assessed very differently from a new FPGA configuration.
- Design unit
- A language unit that can be analysed independently. In VHDL, examples include entities, architectures and packages; one source file can contain several units.
- Library
- A logical namespace for compiled HDL units. The library name, physical location and search configuration must remain consistent between project steps.
- Compilation
- Analysis of source files for a tool. It checks language and semantic relationships but does not yet execute a complete testbench run.
- Elaboration
- Construction of a concrete simulation hierarchy from design units, bindings and parameters. Errors can occur here despite successful file analysis.
- Testbench
- An environment that instantiates the design being tested, generates inputs and observes outputs. A self-checking testbench evaluates expectations automatically.
- DUT
- Design Under Test: the design examined by the test. Choose the DUT boundary deliberately so that interfaces and assumptions are unambiguous.
- Assertion
- An executable statement about an expected condition or property. A violated assertion should produce an understandable failure that can be evaluated.
- Scoreboard
- A checking component that compares observed results with expected results. It needs an appropriate reference model and rules for matching results by time or transaction.
- Linting
- Static examination of source code against selected rules. Diagnostics may concern style, maintainability or potential functional risks and require assessment.
- CDC
- Clock Domain Crossing: the transfer of signals between clock domains. Correct handling depends on factors including signal type, synchronisation and protocol.
- RDC
- Reset Domain Crossing: relationships between regions reset differently. Reset behaviour needs deliberate analysis just as clock boundaries do.
- Code coverage
- A measurement of which defined code elements were reached during execution. Its meaning depends on the specific metric and does not replace checking requirements.
- Functional coverage
- A model of the functional situations relevant to verification. The achieved value is only as meaningful as the selection of objectives being measured.
- Regression
- Repeated execution of a defined set of tests, for example after a change. It reassesses previously tested behaviour and makes new failures visible.
- Seed
- The starting value for a pseudorandom sequence. A recorded seed supports repeatability, provided the tool version and remaining configuration stay the same.
- CI
- Continuous Integration: checking changes together in an automated workflow. For HDL, the execution environment includes tool versions, libraries and licence access, among other things.
From a term to a practical step
To understand how the layers interact, read the workflow from editor to verification. The technical articles explain the background in greater detail; the application notes provide bounded examples with specific checks.